Increasing the speed of operation of electronic devices, such as computer systems, requires increasing the speed of not only processors, digital logic and data storage components, but also the speed of buses used to couple such components together. However, increasing the speed of operation of a bus such that data is transferred across that bus more quickly often entails the use of combinations of transmitter and receiver circuit designs that consume more power. In some cases, this increased power consumption is the result of having to use components in transmitter and/or receiver circuits that have the desirable characteristic of being operated at higher speeds, but which require more power to switch so quickly between states needed to transfer a binary value of 0 or 1. In other cases, this increased power consumption is the result of having to couple together components that have the higher speed characteristic, but which interact with other needed components in ways that may create other undesirable conditions that must be overcome through the use of more power, such as higher parasitic capacitive loads. In still other cases, this increased power consumption is the result of combinations of transmitter and receiver design or referencing to voltage levels such that the transmitters and receivers are required to use the same voltage level as a power rail, even though the core voltage level at which one of the devices internally operates is a lesser voltage.
The fact that the speed of processor, support logic and data storage components have been increased while being necessarily based on differing semiconductor design and/or process technologies has also created voltage level incompatibility issues with processors and digital logic components typically being designed to operate at ever lower voltage levels (currently 1 volt or less), while data storage components, especially dynamic random access memory (DRAM) devices typically operate at higher voltages (currently 1.3 volts or higher). This mismatch in voltages arising from differing semiconductor process technologies typically results in processors and/or digital logic components having to employ transmitter circuit designs that not only transmit data across a bus to data storage components, but which also internally convert from the lower core voltage within a processor or digital logic component to a higher external voltage that matches the I/O voltage employed by a data storage component, because prior art transmitter and receiver circuits often do not work correctly unless both the transmitter and receiver circuits employ the same voltages, themselves. To support this conversion between voltages, a processor or digital logic component must be coupled to two different voltage rails, one for the core and the other for transmitters and/or receivers, must either use special high voltage tolerant transistors to handle the higher voltage within the lower voltage silicon technology which increases process technology costs through added process complexity, or use cascode transistor techniques to handle the higher voltage which increases costs through taking up more space on a silicon die. The detrimental effects of higher power consumption and higher silicon technology costs arising from such approaches where both transmitters and receivers are required to operate at the same higher voltage are incurred regardless of whether the signaling across a bus between transmitter and receiver circuits is entirely single-ended, entirely differential, or a mix of the single-ended and differential.
These difficulties with voltage level incompatibility in current practice are illustrated by FIGS. 1a, 1b and 1c depicting prior art transmitter and receiver circuit designs. It should be noted that although for the sake of simplicity of discussion, FIGS. 1a–c depict only unidirectional configurations, these same issues arise and apply to bidirectional configurations, as well. In FIG. 1a, transmitting device 120 (such as a memory controller IC) employs multiple ones of single-ended transmitter 130 (although only one is shown for sake of clarity) to transmit addresses, commands and/or data across bus 150 to single-ended receiver 170 employed by receiving device 160 (such as a memory IC). Switches 131 and 139 receive data from other portions of transmitting device 120 and drive either a high or low voltage level onto a signal line of bus 150 through resistors 132 and 136, respectively, while resistors 172 and 176 are employed by receiving device 160 to terminate this same signal line of bus 150, referencing receiver Vcc and ground, respectively, at or near the point at which this same signal line is coupled to the input of single-ended receiver 170. Capacitors 134 and 137 are parasitic capacitors, i.e., capacitive loads arising from the connection of switches 131 and 139 to this same signal line of bus 150, thereby slowing down the speed at which the signal state of this signal line may be changed in transmitting data. The presence of resistors 132 and 136 does mitigate this undesirable effect on this signal line, but only to a limited extent, since mitigation to a greater degree would require a higher resistance value which would, in turn, defeat the ability of switches 131 and 139 to drive this signal line. Also, it is common for single-ended transmitter 130 to be designed to conform to a specification of electrical characteristics for a signal line, including signal line 150, such that the resistance of resistors 132 and 136 is often dictated by such a specification, and therefore, cannot be changed. Another undesirable effect of this configuration of transmitter and receiver design is that transmitter Vcc and receiver Vcc must be of the same voltage level for high and low values that distinguish between binary 1 and 0 values to be correctly detected by single-ended receiver 170.
FIG. 1b depicts a somewhat different design for single-ended transmission of data from FIG. 1a, but despite the design differences, largely the same previously discussed problems are presented again. Capacitor 137 again depicts a parasitic capacitor on a signal line of bus 150, again slowing the speed at which the state of that signal line may be changed, and again, the configuration of transmitter and receiver design requires that transmitter Vcc, the receiver Vcc and the power rail to which termination may be coupled must all be of the same voltage level. The same difficulties would continue to exist even if transistor 139 were coupled to a transmitter Vcc and resistor 172 were coupled to ground. Furthermore, despite the depiction in FIG. 1c of a differential receiver in contrast to the use of single-ended configurations in FIGS. 1a and 1b, the same difficulty of differential receiver 180 needing to be supplied with a receiver Vcc that matches the same voltage level as supplied to whatever differential transmitter may drive the pair of signal lines received by differential receiver 180 from across bus 150 still exists.